Silicon carbide (hereinafter referred to as "SiC") has a wide band gap, and its maximum breakdown electric field is larger than that of silicon (hereinafter referred to as "Si") by one order of magnitude. Thus, SiC has been highly expected to be used as a material for power semiconductor devices in the next generation. Up to the present, various types of electron devices, in particular, those for switching large power at high temperatures, have been developed, using single-crystal wafers, such as 4H--SiC and 6H--SiC. These crystals are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Also, some semiconductor devices have been fabricated using crystals of beta-phase SiC, such as 3C--SiC. Recently, power devices, such as Schottky diodes, vertical MOSFET, and thyristors, and CMOS-IC as the most typical semiconductor devices, have been fabricated using SiC as a semiconductor material, and it has been confirmed that these devices exhibit far better characteristics than conventional Si semiconductor devices.
The present invention relates to a MOS semiconductor device having a MOS type gate. Some examples of known Si MOSFET and SiC MOSFET will be now described.
FIG. 4 is a cross-sectional view of a unit cell of typical Si vertical MOSFET that has been generally used as a power semiconductor device. In the Si vertical MOSFET of FIG. 4, an n drift layer 11b having a high resistivity is laminated on an n.sup.+ drain layer 11a, and a p base region 12 is formed in a selected area of a surface layer of the n drift layer 11b, while an n.sup.+ source region 13 is formed within the p base region 12. A gate electrode layer 16 made of polycrystalline silicon or polysilicon is formed on a gate insulating film 15, over the surface of the p base region 12 interposed between the n.sup.+ source region 13 and an exposed surface portion of the n drift layer 11b. A source electrode 17 is formed in contact with surfaces of both of the n.sup.+ source region 13 and p base region 12, and a drain electrode 18 is formed on the n.sup.+ drain layer 11a on the rear surface of the n drift layer 11b. As shown in FIG. 4, the source electrode 17 is often extended over the gate electrode layer 16 via an interlayer insulating film 19. A gate electrode made of metal is held in contact with the gate electrode layer 16 at a portion that is not illustrated in the figure.
In the operation of the vertical MOSFET as described above, when a positive voltage is applied to the gate electrode, an inversion layer appears in a channel region 20, namely, a surface layer of the p base region 12 located right under the gate electrode layer 16, so that current flows between the source electrode 17 and the drain electrode 18 through the inversion layer. If the positive voltage stops being applied to the gate electrode, the inversion layer of the channel region 20 disappears, and the current stops flowing through the channel region 20.
Thus, the channel region 20 plays an important role in the above operation, and its length is desired to be strictly or accurately controlled. To this end, a method called diffusion self alignment (that may be abbreviated to DSA) is employed in the manufacture of Si MOSFET, and the resulting MOSFET may be called double diffusion MOSFET.
Main process steps for manufacturing the double diffusion MOSFET will be now described, referring to the cross-sectional views of FIG. 5(a) through FIG. 5(f) showing the respective steps.
In the step of FIG. 5(a), an n drift layer 11b having a high resistivity is laminated on an n.sup.+ drain layer 11a by epitaxial growth, to provide a Si wafer, which is then subjected to thermal oxidation so that a gate oxide film 15 is formed on the n drift layer 11b. Thereafter, a polysilicon film 1 is deposited on the gate oxide film 15 by low-pressure CVD method.
In the next step of FIG. 5(b), the polysilicon film 1 is patterned by photolithography, to thus form a gate electrode layer 16, and boron ions 2a, or the like, for forming a p base region 12 are implanted, using the gate electrode layer 16 as a mask. In FIG. 5(b), reference numeral 2b denotes boron atoms thus implanted. Thereafter, heat treatment is conducted so as to form the p base region 12, as shown in FIG. 5(c).
In the next step of FIG. 5(d), arsenic ions 3a, for example, for forming an n.sup.+ source region 13 are implanted, using the gate electrode layer 16 and a photoresist 7 as masks. In FIG. 5(c), reference numeral 3b denotes arsenic atoms thus implanted. Thereafter, heat treatment is conducted again, so as to form the n.sup.+ source region 13, as shown in FIG. 5(e).
In the next step of FIG. 5(f), boron/phosphorous/silica glass (BPSG) is deposited on the structure by plasma CVD method, to provide an interlayer insulating film 19, and a window or hole is formed through the insulating film 19 by photolithography. A metal that provides an electrode is deposited on the Si substrate, and patterned so as to form a source electrode 17 and others, as shown in FIG. 5(f). Thereafter, a drain electrode (not illustrated) is formed on the rear surface of the Si substrate, and the manufacturing process is completed.
While a high-concentration p.sup.+ well region that overlaps the p base region 12 may be provided in the structure of FIG. 5, such a p.sup.+ well region can be formed by implanting impurity ions using the gate electrode layer 16 and photoresist as used for forming the n.sup.+ source region 13, and then conducting heat treatment.
What is important in the above process is that the polysilicon film 1 that provides the gate electrode layer 16 is used as a mask during ion implantation for forming the p base region 12 and the n.sup.+ source region 13. Since the p base region 12 and n.sup.+ source region 13 use the same mask, there arises no variations in the position of the mask, and the dimensions of the channel region 20 formed in a portion of the p base region 12 right below the gate electrode layer 16 are accurately and uniformly controlled due to lateral diffusion of impurities during formation of the p base region 12 and n.sup.+ source region 13.
The channel dimensions that influence the characteristics of the MOSFET can be controlled with high accuracy by introducing p type impurities and n type impurities into selected regions using the same mask, and causing thermal diffusion. Thus, the diffusion self alignment method (DSA method) makes it possible to produce high performance MOSFET with a high yield.
On the other hand, SiC is a semiconductor material that is highly expected to be applied to power devices in the future, and its important applications include vertical MOSFET. For example, trench type or planar type vertical MOSFETs have been fabricated using SiC.
FIG. 6 is a cross-sectional view showing a part of a unit cell of SiC vertical UMOSFET as one example of MOSFET (as disclosed in Weitzel, C. W. et al.: IEEE Trans. on Electron Devices, vol. 43, No. 10, pp. 1732-1741 (1996), Agarwal, A. K. et al: Abstract of Int. Conf. Silicon Carbide, III-nitrides and Related Materials (1997) pp. 156-157).
In the SiC vertical UMOSFET, an n drift layer 21b and a p base layer 22 are laminated on an n.sup.+ drain layer 21a, and an n.sup.+ source region 23 is formed in a surface layer of the p base layer 22. A trench 8 that extends from the surface of the n.sup.+ source region 23 down into the n drift layer 21b is provided, and a gate electrode layer 26 is embedded in the trench 8, with a gate insulating film 25 interposed between the electrode layer 26 and the wall of the trench 8. A source electrode 27 is formed in contact with both of the n.sup.+ source region 23 and p base layer 22, and a drain electrode 28 is formed on the rear surface of the n.sup.+ drain layer 21. Also, a gate electrode made of metal is formed in contact with the gate electrode layer 26 at a portion that is not illustrated in the figure.
With this arrangement, when a voltage is applied to the gate electrode, an inversion layer appears in a surface layer of the p base layer 22 that faces the gate electrode layer 26, and current flows between the source electrode 27 and the drain electrode 28 through the inversion layer. By removing the voltage applied to the gate electrode, current flow between the drain electrode 28 and the source electrode 27 is cut off or interrupted, thus showing a switching function.
Since it is considerably difficult to form deep impurity regions in the SiC substrate utilizing thermal diffusion, a large number of UMOSFETs of the above type in which the gate electrode layer 26 is embedded in the trench 8 have been fabricated.
FIG. 7 shows one example of planar type SiC vertical MOSFET having no trench (as disclosed in Shenoy, J. N. et al: IEEE Electron Device Lett. Vol. 18, No. 3, pp.93-95 (1997)).
In the planar type SiC vertical MOSFET, an n drift layer 31b is laminated on an n.sup.+ drain layer 31, and a p base region 32 is formed in a surface layer of the n drift layer 31b by implanting ions at a high acceleration voltage. An n.sup.+ source region 33 is formed in a surface layer of the p base region 32. A gate electrode layer 36 is formed on a gate insulating film 35, over the surface of the p base region 32 that is interposed between the n drift layer 31b and the n.sup.+ source regions 33. A source electrode 27 is formed on the surfaces of the n.sup.+ source region 33 and p base region 32, and a drain electrode 38 is formed on the rear surface of the n.sup.+ drain layer 31 a.
In this example, the p base region 32 having a large junction depth is formed through ion implantation with a high acceleration voltage, and the length of a channel region 40 is controlled using two types of mask, i.e., a mask for ion implantation for forming the p base region 32, and a mask for ion implantation for forming the n.sup.+ source region 33.
In the operation of the MOSFET of the above type, when a positive voltage is applied to the gate electrode, an inversion layer is induced in a surface portion of the n channel region 40 right below the gate electrode layer 36, so as to allow current to flow from the drain electrode 38 to the source electrode 37.
Although the SiC vertical MOS semiconductor devices are expected to exhibit remarkably excellent characteristics, actual SiC devices have not achieved such excellent characteristics, or such devices have not been actually manufactured. One of the reasons is that the self alignment process that enables fine dimension control has not been developed in the process of manufacturing the SiC devices, and accurate control of the channel density has not been realized.
In Si substrates, p type impurities and n type impurities are introduced into selected regions using the same mask, and then thermally diffused so as to achieve a desired channel density with high accuracy. Namely, the dimensions of channels that greatly influence the characteristics of MOSFET can be controlled with high accuracy, thus assuring a high yield in the manufacture of MOSFET.
On the other hand, impurities introduced into SiC by ion implantation hardly diffuse, and therefore the double diffusion MOS (D-MOS) structure as employed in the Si devices cannot be easily realized in the SiC devices, thus making it difficult to control the channel density with high accuracy. Since p type impurities and n type impurities are introduced using separate or respective masks, the resulting SiC MOSFET has large channel resistance with considerably large variations. The ON resistance of the device as a whole is mostly determined by the channel resistance, and thus the SiC devices fabricated so far have not taken advantage of inherent characteristics of SiC as expected.
The impurities introduced into SiC through ion implantation are less likely to be activated, namely, the impurities thus introduced have a poor activation rate. In order to improve the activation rate, the ion implantation needs to be conducted at a high temperature of 1000.degree. C. or higher, and therefore a resist cannot be used as a mask for ion implantation. Also, heat treatment for activating the implanted impurities needs to be conducted at a high temperature of 1500.degree. C. or higher, thus causing a problem that oxide films and polysilicon cannot withstand the heat treatment.